A clock divider circuit is a circuit that transforms an input signal of a frequency f to an output signal of frequency (f/K), where K is an integer. Clock dividers find wide usage in digital modules that include components that require clock signals of more than one frequency. Using separate clock generators for the various required clock frequencies would result in an increase in area and complexity of the clock generator module. To avoid this problem, the clock generator module typically contains only a single clock generator that provides a clock signal having the highest frequency of any of the required clock signals. Lower frequency clock signals are obtained by means of a clock divider in the digital module. There has been a need for a clock divider that requires minimal integrated circuit surface area and that can divide multi-phase clock signals with minimal circuit complexity.